The field of the invention generally relates to clock recovery systems for high speed data communications, and more particularly relates to an integrated CMOS circuit that includes transmitter and receiver sections wherein the receiver section provides fast clock acquisition of an incoming data signal.
As is well known, high speed data is usually transmitted and received in a non-return-to-zero (NRZ) format to minimize distortion by reducing the high frequency content of the signals. For example, consider a string of incoming data 10010 in a NRZ format at a 200 Mbit/sec rate where each bit uses a full period of 5 nanoseconds. Normally, the data clock is not transmitted along with the data because an additional line or channel would generally be required. Therefore, in a typical clock recovery system, the receiver uses the incoming data to generate a clock, usually referred to as the "recovered clock", at exactly 200 MHz, and the recovered clock is aligned with respect to the incoming data. For example, it is desirable that the positive transitions of the recovered clock occur at the exact middles of the data bits where one would expect the maximum voltage if the received bit is a logical "1", or the minimum voltage if the received bit is a logical "0". Once the clock is recovered, the NRZ signals and the recovered clock are fed to respective "data" and "clock" inputs of a flip-flop that functions as a decision device. That is, the flip-flop will be clocked by the recovered clock, and the output will be the recovered data in a clean "1" or "0" state.
Since the desired clock frequency does not appear in the frequency spectrum of the NRZ data, a non-linear operation is normally applied to the incoming data to generate a frequency component containing the clock frequency. In a typical prior art approach, the incoming NRZ data is delayed by 90.degree. in a phase shifter, and the original and delayed NRZ data are fed to an exclusive 0R (XOR) gate. As is well known, the output of the XOR will have a frequency component corresponding to the originating or desired clock. The output of the XOR is then fed to a phase detector along with the output of a voltage controlled oscillator (VCO) or current controlled oscillator (CCO). The phase detector and the VCO or CCO are part of a phase-locked loop. That is, the output of the phase detector is used to generate a control voltage or current to the VCO or CCO such that the VCO or CCO is finally brought to oscillate at the same frequency and phase as the originating clock of the incoming NRZ data. However, the VCO or CCO output can not be used to clock the decision device or flip-flop because it is not aligned at the optimum decision point at the middle of the bit period. Thus, it is generally necessary to generate a second clock that is 90.degree. out-of-phase or is in quadrature with the VCO or CCO output. This quadrature clock is then used to clock the decision device, and it catches the NRZ data at the optimum decision points at the exact middles of data bits.
In high frequency data communications, there is generally a requirement for fast acquisition of incoming data. That is, it is desirable that the clock be recovered and aligned with the incoming bits of data after only a short acquisition time using a relatively short preamble at the beginning of the transmission. For example, a typical system may have a requirement that an initial preamble of no more than 1000 bits be used to recover the clock and align it with the incoming data. However, incoming NRZ data is usually very noisy. Therefore, a clock recovery system that uses a phase-locked loop to recover the clock must have a relatively low bandwidth to minimize jitter and operate reliably. As is known in the art, it is difficult to attain a low bandwidth and still provide short acquisition times.
As is well known, a frequency detector is generally slower than a phase detector, and also malfunctions when one of the input waveforms has missing transitions such as would typically be the case with data (i.e. anytime the data was other than alternating 1s and 0s.) Thus, as described earlier herein, a phase detector is used to compare the output of the exclusive OR and the output of the loop oscillator. However, phase detectors generally perform poorly when the two input frequencies are initially far apart from each other, and relatively long acquisition times may result. That is, it may take a relatively long time and a relatively large number of bits before the loop oscillator is brought to the frequency of the originating or desired clock, and the phase is adjusted to align the quadrature clock with the incoming data.